Binary magnetic storage devices of the matrix type



Jan. 22, 1963 B, J, WARMAN ETAL 3,075,183

BINARY MAGNETIC STORAGE DEVICES OF' THE MATRIX TYPE REWE/ff E zr nz 'I D/e/Vf COPE COU/WEP C/PcU/ l lLn T1; A.

INVENTORS I 5i @.2 BLooMFIELn JAMES WABMAN LIAM BERNARD DELLER mi ggurtqv Jan. 22, 1963 B. J. wARMAN ETAL BINARY MAGNETIC STORAGE DEVICES OF THE MATRIX TYPE Filed Aug. 2'7-I 1959 lNnO XH INvENToRs BLOOMFIELD JAMES WARMAN WILLIAM BERNARDDELLER Jan. 22, 1963 B. J. wARMAN ETAL 3,075,183

BINARY MAGNETIC sToRAGE nEvIcEs oE THE MATRIX TYPE Filed Aug. 27, 1959 4 Sheets-Sheet 5 DP/V/NG CURE 55 CON WOL c//acu/r To DCf ToDCg T0065 Jan. 22, 1963 B. J. wARMAN ETAL 3,075,183

BINARY MAGNETIC STORAGE DEVICES 0F THE MATRIX TYPE Filed Aug. 27, 1959 4 Sheets-Sheet 4 DPM/E L To 5109MB, com or I' ,2,

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BLOOMFIELD JAMES WARHAN WILLIAM BERNARD DELLEB 3,675,133 ENARY MAGNETEC SRGE BEY/'ICES GF 'EEE MATER TYPE Bloomfield Staines Warrnan, tlharicon, and Wiliam lernard Reiter, Mottineharn, Loudon, England, assignors to Associated Eiectrrcai )industries (Woah/vieil) Limited, a company of Great Britain Filed 27, i959, Ser. No. 835,515 Ciaims priority, application Great Britain Sept. 2, 195g S tlainxs. {Cl. 34h-F174) This invention relates to binary magnetic storage devices of the matrix type.

Such stores are well known and usually comprise a number of ferrite cores arranged in one or more matrices usually with separate conductors linked with all the cores in' each row and separate conductors linked with all the cores in each column. The information is stored by reversing the remanent magnetism in the cores by rneans of currents passed simultaneously through the particular row conductor and column conductor linked with the core in question.

During reading interrogation currents are passed along the appropriate row and column conductors. These interrogation corren s are in the reverse direction to the writing currents and, assuming the arrangement is such that the core is set (ie. reversed) tor a l but is not set for a then action of the interrogation currents is such that if the inorrnation in the core in question, represents a 0, then there is no reversal of magnetism i.e. no resetting during sending. lf however, the core is storing a l, then the interrogation currents will reset the core and this will induce a signal in an output conductor which is linked with all the cores in se i it will be appreciated that with such arrangements, vhen either writing or reading, the values of the line and column currents must be so chosen that individually they are incapable ot reversing a core, so that they do not reverse any of the other cores in the same line and colas the selected core. However the combined action or" the line and column currents at the point or" intersection rnust be suliicient to etiect this. ln this way selection or a required core is carried out.

it Ifollows, therefore, that both the uniting currents and the interrogation currents must lie within certain specified limits. ln the case of the writing currents this does not cause difficulty since they are only required to set the cores. However, in the case of the interroga -on currents it would be desirable to pass large currents through a selected core in order to obtain a large output signal. rl`his is desirable for the reason that the selected row and column all the cores which are being interrogated, though not be actually reversed, will have their magnetism varied and these will cause mall signals to be induced in the output conductor and in cases Where there are a number of cores in a line and column these signals may add up and cause spurious signals which cause difficulty in the discr nation of the Wanted signal at the output line. Whilst the effects of these spurious signals can be reduced to some extent by threading the output conductor through the cores in alternate directions in chosen rows columns, nevertheless it is difficult to reduce them suticiently and the read circuit must then discriminate for outputs or both polarity.

The main object of the invention is to provide a simplified arrangement which gives satisfactory discrimination of output signals in a binary matrix store.

According to the present invention a binary matrix store comprises fa matrix array of two-state magnetic storage cores together with two-state magnetic driving cores associated with each column (or row) of storage cores and a read/write blocking oscillator circuit as- A. dildd Patented dem 22, i963 sociated with each row (or column) the arrangement being such that during reading a selected drive core is actuated to the set state so that storage cores of the associated column (or row) which are already in the re-set state are changed to the set state whereby the blocking oscillators ot the associated rows (or columns) are triggered and by their regenerative action provide an amplified and lengthened output signal and by their degenerative action revert to the untriggered state concurrently with the re-settinc of the column (or row) drive core thereby re-setting those storage cores which during reading were set. l't will be appreciated that the regenerative action of the blocking oscillators amplities and lengthens the read current pulses from the associated columns (or rows) thereby providing directly usable output signals. The subsequent degeneration provides a rewrite current for the core stores.

Additional means may be provided for triggering a selected blocking oscillator or preventing the oscillator triggering during re-writing so as to change the information which is :fe-written into the matrix store from that which was read out from it.

According to a preferred arrangement the blocking oscillators comprise saturating transistor circuits with means for applying a tiggering voltage independently of the core store to trigger the blocking oscillator and means for applying a voltage to prevent the blocking oscillator being triggered oy signals from the core store. Preferably each blocking oscillator includes a coupling transformer whereby it is coupled to the storage cores and a feedback transformer having its secondary winding connected in series with the secondary of the coupling transformer so that the induced current due to feedback assists the induced read current from the core store.

The driving cores of the core store function' las current transformers whereby the storage cores are stimulated by a reading current of large amplitude and improved discrimination obtained. Moreover, during reading, the magnetic condition of the driving core is reversed (i.e. changed from the rc-set to the set condition) thereby en'- abling the driving core to retain a memory of the group read.

Rewriting information back into the core can be performed on a halt current basis in two co-ordinates one of which is formed by the read out circuit from the storage cores whiles the other is formed by the drive circuit from the driving core into the storage cores. Thus the same conductors can be used for re-writing as are used for reading. The half current in the drive circuit in such arrangements can be obtained by passing a re-write signal through all the drive cores in series in a direction to change the one set core back to the re-set condition (all other drive cores already being in the re-set condition).

T he storage core output signal responsive circuits each take the form of -a regenerative blocking oscillator circuit adapted to perform the functions of both reading the output signals from the storage cores and writing information back into the cores. The half current in the read out circuit can in such cases be obtained as a result of the regenerative action of the blocking oscillator output signal responsive circuit extending the duration and increasing the amplitude of the output signal obtained from the storage cores during reading.

he storage cores may be arranged to form a matrix each group with its drive core forming a column (or row) and the output lines the rows (or columns). A number of such matrices may be stacked to form a three dimensional array and a particular matrix may be selected by passing a hold off current through the drives cores of all the matrices except the selected one which is left in an operative condition, ie. capable of reading and Writing.

Provision may he made for the sequential scanning of the core storage groups in a selected matrix by means of a counting circuit arranged to step cyclically and effecting reading and writing operations alternately during each step of the counting circuit. In such cases the counting circuit would first set a group of storage cores for reading and then reset itfor writing and then perform the same sequence vwith'the next group. Y

The counting circuit stages may be'connected to correspending drive cores-of each matrix but will have no eect onfmatrices otherthan the selected matrix.

Similarly. the same output conductors may be linked with corresponding rows (if the columns are groups or vice versa) of all the matrices so that only one set of read write circuits is required. Here again only a selected matrix would'be operative at any one time.

Clearly the information passed from a core may be changed externally and` it does not follow that the information re-written will-be the same as that whichv was readout.

In addition to the cyclical'operations bythe counter circuit provision may be made for random access to the core storage'groups using a separate randomaccess drive core with, and a third wire'interlinking, the cores of eachV core storage group.

Preferably means are provided for interlacingthe random and sequential access to the core storage groups.

inorder that the invention may be more clearly understood reference will now be made to the accompanying drawings, Yin which: f

FIG. l is a simpliheddiagram explaining the action of asingle matrix;

FIG. 2 shows a blocking oscillator arrangement which can form the basis ofY the Read/Write circuit; l

PEG. 3 shows how a number of matrices can be stacked to form a store; A

FIG.- 4 shows-a circuit suitable for one stage of the counter;

FIG. 5 yshows a coding circuit which can be used in con-V junction with FIG. 4;

FIG. 6 shows a suitable circuit Vfor-the column counter.

FIG. 7 shows a suitable arrangement for the selector circuits, and

FIG. 8 shows one form of Read/Write circuit.

FIG. l Vis a diagrammatic view illustrating the principle underlying theinvention and shows a matrix formed of ve rows and tive columns. It will be appreciated'that normally there will be a number of such matrices in a store, as'will be explained subsequently. At the junction of each ofthe row conductors Li-L'S and columns C11-CS isa ferrite storage core. At the right hand ends-of each of lthe rows-are indicated the reading and writing circuits R/Wl to R/WS.4 Below the storage cores are shown a row'v of driving cores DRI-DRS. The right hand coil of eachof thesei's connectedto a column conductor and the lower coil is connected'to the appropriate stage of a iivev stage counter circuit. The upper-'windings of the driving-cores are connected in series with a control circuit 'and' the left handrwindings to a re-write circuit.

In operation a current would normally pass through the control circuit to hold all the driving cores biased to an oi state in which they are inoperative. When a particular'matrix is to be put into operation the current through the control circuit is removed so that all thedriving cores of the particular matrix in question are operative. The counter circuitV at the foot of the ligure passes a read current through each column of storage cores iny turn. Thus, when a current from stage l of the counter circuit passes through the bottom winding of the driving core DRI,T this core will be turned over to the set state. In turningE over Vitv will induce a read current in the column conductor C1 and this will affect all' the storage cores in the first column. if they areholding asignal, say a 1, then they will be turned over but there will' be no action if they are holding nosignal, i.e. if they indicate a 0, If 'ai storage coreis holding a l, a signal willbe fed the example under consideration. The turning over of Dil will send a current along the column conductor in the reverse direction so as to assist in turning bach any of the cores to which a signal is being fed from the associated read/write circuits which current will be timed to coincide with the re-write signals.

This sequence of operations will then be repeated with column C2 and so ou.

It will be appreciated that with this arrangement during reading, `a large read current can be passed from the driving core through 4the storage cores so as to obtain a large output signal. Provision for selection is unnecessary as the read current passes through only the storage cores of the group which is being read and'each of the cores of this group is connected toY aV separate read/write circuit.

At the same time interference withstorage cores in other columns is avoided since during reading .the drive co-res turn over sequentially one at a time so that only one of the drive cores will provide a signal at -any given time, and similarly, since rte-writing alternates with reading, only the driving core which was turned over during reading can be turned back to its original state.

It will be appreciated also that in the above operation reading and writing of each of the columns will occur cyclically under the control of the driving core counter circuit.

Cases may arise in'which it is desired to write a signal into a selected storage core and to enable this to be carriedl out there is a set of ran-dom access driving cores at the top of FlG. l designated Rial-RAS. These are associyated with respective columns of storage cores in the same way as the driving cores shown at the foot ofthe column.

In order to ywrite into a selected co-lumn of cores a current is passed through the top winding of the appropriate random driving core from one of the sources shown as SLI-SLS causing the random driving core-to set and pass a read out signal through its associated storage cores causing these to send output signals to their associated read/ write circuits thus clearing the storage. Theappropriate random driving core has now been set and the associated storage cores cleared of markings (i.e. all are in the Ie- `set (O) state). A re-write pulse is now applied to the bottom windings of the random driving cores and co-incident with this, the read-write circuits are stimulated to adopt the new pattern of information which it is required to insert into the core storage group. The random driving core being re-set by the re-write current passes a half current to the cores of its associated group a further half current being obtained from the read/ write amplifiers in accordance with the required storage pattern and the combined eect of these two currents sets `the core storage group to the new pat-tern.

Alternatively, if it may 'be assumed that the storage group is already clear then the random drive core associated with the column can be set -by a small current which does not set the storage cores and then a pulse can be applied to the rewrite line and simultaneously 4a signal applied from the tread/write amplifier to write a pattern of information into the selected storage cores.

It will be appreciated that the operation of random access cores is exactly the same as that of the driving cores excepting that they are not operated cyclically. Means, however, should preferably be provided to ensure that'the random access cores are only operated between the times that the driving cores are operated bythe counter circuit to avoid any contliction and inaccuracies,

Each of the read/ write circuits preferably comprise 'a transistor `blocking oscillator and a convenient form of this is shown in FG. 2. l'f a small pulse is read out from one of the storage cores in th-e row concerned this will occur across the winding A which is the primary winding of transformer Tl. A stepped up voltage will appear across the winding E suflicient to cause `the emitter voltage of the transistor Si to rise above the bias voltage.

The transistor S1 then begins to conduct and the collector voltage rises towards earth. The rise in collector voltage is coupled back via T2 to the emitter in such a way as to cause S1 to pass an increased current. The action then becomes re-generative, the collector voltage rising rapidly to earth and the collector current rising progressively during the duration of the pulse until the transformer is saturated. The increase in current necessary to assist the voltage across the winding D cannot then be supplied by the transistor and the collector voltage falls. rhis action is again re-generative Vand the transistor is rapidly cut off to terminate the pulse. During the pulse the emitter cunrent passes through winding B and induces a stepped up current in winding A in such a direction as to tend to cause the storage core, which triggered the oscillator by turning over, to turn back to its original state. rl`his pulse from the blocking oscillator will coincide with a pulse along the column conductor from the core in question obtained through the re-setting of the driving core associated with that column and thus the storage core in question will be turned back and the information thereby re-written into it.

An important feature of this arrangement is the use of the two transformers Ti and T2 with the secondary C of the feed-back transformer T2 connected in series with the secondary of the coupling transformer Tl and in such a direction that the induced current in C due to feed back assists the read current induced in B by the storage core which is being read.

it will lbe appreciated also that information can be written into a specified position in the store during the cyclicoperation by triggering the blocking oscillator with a positive pulse on the emitter at the appropriate time in the case of a l or raising the positive bias on its base to prevent the triggering in the case of the 0.

These actions must, of course, coincide with the resetting of the appropriate driving core or writing core.

In order to allow time to rocess stored information, i.e. perform computations etc., the half re-write pulse should preferably be timed to occur near the end of the blocking oscillator pulse. The information can then 'be read out of the core, `and if it is wished to change a 0 to a l then the blocking oscillator can be triggered; if it is required to change a l to a O then the blocking oscillator can be quenched. In either case this must be done prior to onset of the rewrite pulse.

It will be understood that when a blocking oscillator changes from its reading to its re-writing function it must reverse the voltage which was developed across its input by the applied read signal current. ln addition by its regenerative action the blocking oscillator must amplify and lengthen the duration of the read current signal, so that the read and write drives applied to the storage cores can follow one another. With the proposed blocke ing oscillator using direct transformer feedback between the collector and. emitter electrodes of the transistor, since the read current signal applies a positive potential to the emitter electrode to cause the transistor to conduct the ohmic voltage drop across the secondary of the feedback transformer due to the initial current How in the emitter circuit drives the emitter end of this winding negative with respect to its other end. The initial curl rent Jdow through the transistor initiates the regenerative action of the circuit and the positive going voltage pulse transformer is induced into the secondary winding as to' drive the emitter end of this winding positive, the secondary feedback winding now acting as the generator to maintain and amplify the flow of emitter current. In this Way the blocking oscillator automatically reverses the voltage developed across the secondary of the feedback transformer. The regenerative action continues until the feedback transformer is saturated when the increase in current necessary to sustain the voltage across the primary of the feedback transformer cannot be maintained and the collector voltage begins to fall, thus initiating a degenerative action which rapidly drives the transistor to cut-off to terminate the pulse. To achieve the required voltage change in the emitter circuit due to the read out signal from the matrix and also to achieve the required current amplification for rte-writing back into the matrix a separate coupling transformer is used having a primary to secondary step up ratio to provide the required voltage step-up in the forward direction of the transistor and also to provide a step down ratio in the reverse direction to provide the required current amplification. The blocking oscillator will be further described.

FIG. 3 shows how a store can be constructed of a number of matrices of the kind shown in FIG. l stacked one over the other. The matrices are indicated as Ml, MZ, M3 and Mn. In order to simplify the drawing each matrix is shown with two rows of storage cores only though in actual practice there would be a considerably greater number. rfhe matrix counter circuit shown on the left controls the control circuits of the driving cores and passes currents through the matrix control lines CM1, CM2 so as to bias all the driving cores to an off or inoperative state except those of a selected matrix in which the driving cores would be rendered operative and the action of the matrix counter circuit is to render each of the matr`ces operative in turn. The drive core counter circuit, as explained in connection with HG. l, operates each driving core of the selected matrix in turn. circuit from the counter circuit, however, includes windings on all the corresponding driving cores of each matrix.

Thus, the first stage will include all the first driving cores which, in the actual construction, are arranged one over the other. However, dri-ving cores of the matrices other than the one concerned will be held inoperative by the matrix counter circuit. Thus, each matrix will be selected in turn. At the top of HG. 3 is shown the random access column selector and at the right is shown the random access matrix selector.

As explained previously, the matrix selector will select the appropriate matrix and the column selector will select the required column in the selected matrix.

It will be observed that the column counter and column selector are connected with a corresponding column in each matrix.

Thus, the rst stage of the column counter is connected to the DCI driving core of each matrix and similarly the first stage of the RA column selector is connected to the RAll core of each matrix.

it will also be noted that the read/write lines connect all the storage cores of corresponding lines in series. Thus, the line Ll connects all the first lines of each matrix in series to a common read/write circuit.

FIG. 4 shows a suitable circuit for a stage of the matrix counter. The circuit shown comprises two transistors S2 and S3 which are cross connected to form a bi-stable circuit. At any instant one of the transistors will conduct and the other be cut off. Successive pulses applied to the input terminal will cause the circuit to alternate between the two states and on alternate changes pulses will be applied from the output circuit to the input of the next stage. The points marked M, M' can be connected to pass the control signal to select the matrix.

The matrix counter Will be stepped forward one by a puise applied from the column counter each time the latter reaches the end of a count.

One way of applying the control signals is by means The p of the coding circuit shown in FIG. 5, of which there will be one for cach matrix. This` arrangement assumes a four stage. counting circuit andthe stages will be connected respectively to the diodes D1, D2, D3 and D4. Depending upon which side of the bi-stable circuit they are connected they can be made to respond to a or a 1. In accordance with an appropriate code the transistor S4 will controi S5 so that it is held on or off, and inter4` rupts the current through the driving core controlcircuit of the matrix associated with thecoding circuit concerned'. S4 and S5 are so` arranged that when S4 is on then S55 is oi and vice versa.

Such an arrangement enables a smallnumber of stages of counter circuit tol operate a larger number of'matrices.

FIG. 6 shows a suitable circuit `for the column counter. This is a sequence'rcircuit using ferrite cores; There are a'series of cores CLjCZ, Cn which operate in sequence andtwo drive circuits operated alternately.

Assuming for a starting position that winding B of C1 is energised so that current'iows to DCI, then'wh'en current ows through. the drive l circuitrcore C1 will turn over; this will causen/pulse to pass through windingY A of C1 Which vwill be ampliedby S6 and^willtlowthrough Winding B of C2 to DCZwhich will pass a read current to its associated cores. Y p 1 l Y At the samev time the current through B of Clwill beV cut orf through the emitter circuits of transistor S6. The

next driving pulse through drive 2 will turn over. C2 andV 'that column 1 'is to be selected then Winding P oi SCI will be energised and current passed through therdrive cir` cuit. A current will then be'inducedin Winding Q and this will pass through the amplier transistor S9-to core RAL FIG. 8 shows-'a suitable read/Writecircuit.k This is a development of FIG, 2 andfthetransistor S1V operates a second transistor S12.

Trigger pulses are applied along/the line marked ""'frig ger; these are appliedrto the emitter ofl S1 and will trigger theicircu-it so that where-a 0 hasbeen read out from the store `a l will be 're-written Whenthe re-write pulse is` appliedlto the column drive'core. Erase pulses are applied along the couductor'marked fErase. These. will quench the oscillator Yso `that in cases in which a 1 has been read a 0 will be re-written.

The output from the `blocking oscillator can conveniently operate a lui-stable circuit which feeds a--1 or -a 0 as the case may be to an arithmetic unit. The arithmetic unit in lturn will apply a pulse to the Trigger or Erase circuit depending upon whether la 1 or a 0 is to be fed into the store.

Whilst the storage cores are separate functionally they' need not be physically separate, but may be formed -by threading'conductons through spaced aperturesin' a ferrite board'in' a manner which is well known.

What we claim is:

1. A binary matrix store comprising'an array of twostate magnetic storage cores located along two sets of irltersecting l-ines -to form a rectangular matrix, ya separate two-state magnetic drive core associatedwith each` individual line of cores of the first set and coupled there-to by a drive core conductor, a-separateV regenerative blocking` oscillator associatedwith eachv line of cores-of the secondv set land coupled thereto -by abloclcing oscillator conductor, means for actuating a lselected drive core to the set state during a reading operation to generate a pulse in the associated drive core conductor which changes to the set state those storage cores coupled Ithereto which are in the 8.. re-set'state, means actuated by the changing of a storage core from the re-set tothe set state to generate a pulse in the associated blocking oscillator conductor which is applied to trigger the associated blocking oscillator, means effective after a predetermined time interval Ito cause a two-state magnetic drive core associated with each indiy vidual line ofcoresrof thejirst set and coupled thereto by a drive Vcore conductor, a separate regenerative blocking oscillatorassocia-ted with each line of cores ofthe second set and coupled thereto by a'blocking oscillator conducttor, means for actuating a selected drive core actuated to the set state during a reading y-operationrtogenerate a pulse in the associated drive core conductor which thereby changes to the set state those storage cores coupled thereto which are fin the re-set state, means actuated by the changing of -a storage core from the re-set to the set state to generate a pulse in` the-associated blocking oscillator oonductor which is applied to trigger the associated blocking oscillator, means effective after a predetermined time interval -to cause `a 'triggered blocking oscillator automatically to revert to its original state and thereby appl-ies a re-set signal `to the same storage core and means for applying a complementary re-set signal concurrently along lthe drive vcore conductor associated with the storage core in' question, means for preventing the triggering of a lblocking oscillator by a storage'core signal and means for triggering'a blocking oscillator independently oi storage core signals t-o re-write into a storage core a signal different from the signal read.

3. A binary matrix'store comprising an array ol twostate magnetic storage cores located along two sets of intersecrting lines yto form a rectangular matrix, a separate two-state magnetic drive core associated with each individual line of cores of the rst set and coupled thereto by a drive core conductor, a separateregenerative transistor blocking oscillator associated with each line of cores of 'the second set Iand coupled thereto by a blocking oscillator conductor, means for actuating ka selected drive core to the set state during a reading operation and thereby generate a pulse in the associated drive core conductor which thereby changes tothe set state those storage cores coupled thereto which-'at that time `are in the re-set state, means actuated by the changing of a stcrage'core from the re-set to the'set state to generate a pulse in the associated blockingroscillator conductor which is applied to'tr'igger the associa-ted blocking oscillator, means effective 'after a predetermined time interval to cause a triggered blocking oscillator automatically to revert toits 'original state and thereby apply a re-set 'signal to the same storage core and means for lapplying a complementary re-set signal concurrently along -the drive core conductor associated with the storage core in question, said transistor blocking oscillators each comprising a regenerative feedback transformer and a coupling transistor coupling the blocking oscillator with the storage core line and `a series connection between 'the transformer secondary windings for ap plying the induced voltage due to feedback to assist the signal from the storage core.

4. A binary matrix store comprising an array of two- Astate magnetic storage cores located alo-ngtwo sets of in terseoting lines to form a rectangular matrix, a separate Ytwo-statemagnetic drive core associated with each indiv-idual line of cores of the lirst'set and coupled thereto by'a drive core conductor, a separate regenerative bloc ing oscillator associated with each line of cores of the second set and coupled thereto by a blocking oscillator conductor, means eiective during a reading operation to actuate la selected drive core to the set state and thereby generate a pulse in the associated drive core conductor which thereby changes to the set state those storage cores coupled thereto which are in the re-set state, means for generating a pulse in the associated blocking oscillator conductor when a storage core is set which pulse is applied to trigger the associated blocking oscillator, means for causing a triggered blocking oscillator automatically to revert to its yoriginal state after a predetermined time interval and thereby apply a re-set signal to the same storage core, means for applying a complementary re-set signal concurrently applied along the drive core conductor associated with the storage core in question and means for preventing triggering of a blocking oscillator -by a storage core signal and means for triggering a blocking oscillator independently of the storage core signal to re-wri-te a signal diierent from the signal read and means for actuating the drive cores sequentially.

5. A binary matrix store comprising an array of two state magnetic storage cores located along two sets off intersecting conductor lines -to form a matrix, a. separate two state magnetic drive core associated with each individual line of the first set Iof core lines and operatively coupled thereto, a separate 'regenerative blocking oscillator coupled to each line of the second set of core lines, means effective during a reading operation for actuating a selected drive core to the set state thereby to generate a pulse in the associated line and reset .all storage cores coupled to said line which are then in the set sta-te, means actuated by the resetting of said storage cores for triggering the associated blocking oscillators, means whereby said blocking oscillators after a predetermined time interval, if unchanged, apply reset sign-als to the same said storage cores, means for resetting said selected drive core to apply a complementary reset signal lto said storage `cores concurrently with the reset signal from the blocking oscillator, means for preventing the triggering of a blocking oscillator by a storage core signal and means for triggering a blocking oscillator independent of storage core signals to rewrite into a storage core a signal diierent from the signal read.

References Cited in the tile of this patent UNITED STATES PATENTS 2,856,596 Miller O'ct. 14, 1958 2,910,674 Wittenberg Oct. 27, 1959 2,917,727 Reach Dec. 15, 1959 2,922,145 Bobech Jan. 19, 1960 

3. A BINARY MATRIX STORE COMPRISING AN ARRAY OF TWOSTATE MAGNETIC STORAGE CORES LOCATED ALONG TWO SETS OF INTERSECTING LINES TO FORM A RECTANGULAR MATRIX, A SEPARATE TWO-STATE MAGNETIC DRIVE CORE ASSOCIATED WITH EACH INDIVIDUAL LINE OF CORES OF THE FIRST SET AND COUPLED THERETO BY A DRIVE CORE CONDUCTOR, A SEPARATE REGENERATIVE TRANSISTOR BLOCKING OSCILLATOR ASSOCIATED WITH EACH LINE OF CORES OF THE SECOND SET AND COUPLED THERETO BY A BLOCKING OSCILLATOR CONDUCTOR, MEANS FOR ACTUATING A SELECTED DRIVE CORE TO THE SET STATE DURING A READING OPERATION AND THEREBY GENERATE A PULSE IN THE ASSOCIATED DRIVE CORE CONDUCTOR WHICH THEREBY CHANGES TO THE SET STATE THOSE STORAGE CORES COUPLED THERETO WHICH AT THAT TIME ARE IN THE RE-SET STATE, MEANS ACTUATED BY THE CHANGING OF A STORAGE CORE FROM THE RE-SET TO THE SET STATE TO GENERATE A PULSE IN THE ASSOCIATED BLOCKING OSCILLATOR CONDUCTOR WHICH IS APPLIED TO TRIGGER THE ASSOCIATED BLOCKING OSCILLATOR, MEANS EFFECTIVE AFTER A PREDETERMINED TIME INTERVAL TO CAUSE A TRIGGERED BLOCKING OSCILLATOR AUTOMATICALLY TO REVERT TO ITS ORIGINAL STATE AND THEREBY APPLY A RE-SET SIGNAL TO THE SAME STORAGE CORE AND MEANS FOR APPLYING A COMPLEMENTARY RE-SET SIGNAL CONCURRENTLY ALONG THE DRIVE CORE CONDUCTOR ASSOCIATED WITH THE STORAGE CORE IN QUESTION, SAID TRANSISTOR BLOCKING OSCIL- 